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CprE 305 : Computer Organization and Design
Spring Semester, 2003
Iowa State University
MWF 9:00-9:50am, Bassey 210

Instructor: Zhao Zhang
Office Hours: Monday 10:00-11:00AM; Thursday 1:00-2:00PM; or by appointment
Office Location: 368 Durham Center
Contact: phone 294-7940, e-mail: zzhang@iastate.edu

Number of Credits: 4
Prerequisite: CprE 211 or ComS 321

Students with Disabilities: If you have a disability requiring accommodation in this class, please notify the instructor at the beginning of the semester.

Important Notice: I reserve the right to make minor changes to the syllabus.

Course Goals

This course introduces you to computer organization and design. You will understand the performance evaluation of computers, the principles of designing the hardware/software interface, a simple implementation of MIPS ISA, and a pipelined implementation of MIPS ISA. You will also understand memory hierarchy and I/O devices and interfaces.

Textbook

Computer Organization and Design: The Hardware/Software Interface, Second Edition, D. A. Patterson and J. L. Hennessy, Morgan Kaufmann, 1997. .

Course Outline.

• Introduction to computer organization
• Evaluating performance
• Instruction set design
• Computer arithmetic
• Processor: Datapath and Control
• Pipelining
• Memory organization
• Interfacing processors and peripherals
• Advanced Topics

HOMEWORK

There will be eleven assignments dealing with exercises in the textbook or provided by the instructor.  No late assignment will be accepted. Students are responsible to pick up the assignment from the class web page. If you need to make any alternative arrangements, contact the instructor.

LABORATORIES

There will be eleven lab assignments provided by the instructor. Labs completed within the lab time will receive 100% credit. Labs not completed within the assigned time will receive 90% credit if demonstrated at the start (within the first 30 minutes) of the following lab time. After that, labs will be penalized 25% per week. Any time after the first 30 minutes is considered the following week.

Attendance is mandatory. Failure to attend lab (or be more than 30 minutes late) will void this policy, and the lab will be considered late as soon as the lab session has ended.

PROJECT

There will be one project in which you will design an instruction set (done as part of one homework) and implement it using a pipelined data path. You will need to demonstrate that the implementation works with test programs that you will write. You will need to write a project report. More details about the project will be given.

EXAMS

• Three quizzes
• Exam 1: TBD
• Exam 2:  TBD

Grading