CprE 305 Homework #10

Reading Assignment: Finish Chapter 6 and Chapter 7.1-7.3.

P1. (30 points) Problem 6.20.

Hint: Consider the lw-sw seuquence
lw $2, 100($5)
sw $2, 200($6)
The sw instruction needs the value of $6 at EX stage but $2 at MEM stage. Since the lw produces the value of $2 at MEM stage, the stall between lw and sw can possibly be avoided in the pipelined execution.

By contrast, the stall is unavoidable for lw-sw sequence like "lw $2, 100($5); sw $6, 200($2)". Also notice that the lw-sw sequence is different from the lw-lw sequence discussed in the class.

P2. (10 points) Problem 6.23

P4. (10 points) Problem 6.24

P3. (10 points) Problem 6.28

P5. (10 points) Problem 6.29

P7. (30 points) Verilog Problem. We will develop the following module at the behavior level. Design a forwarding unit with respective multiplexers to select register input to ALU in ALU stage defined as follows. Note that it consists of only combinatorial logic.

FORWARD(IDEXRA1, IDEXRA2, EXMEMWA, MEMWBWA, EXMEMWRF, MEMWBWRF, IDEXRD1, IDEXRD2, EXMEMWD, MEMWBWD, ALUIND1, ALUIND2).
Here IDEXRA1 and IDEXRA2 are the addresses of the two registers just read from the register file. IDEXRD1 and IDEXRD2 are two 32-bit values that are the contents of the registers read. EXMEMWA and MEMWBWA are the addresses of the registers that could be written by the instructions in those stages. EXMEMWD and MEMWBWD are the corresponding 32-bit data values. EXMEMWRF and MEMWBWRF are the values of the signals indicating if the instructions in those stages will be writing into the register file. Finally ALUIND1 and ALUIND2 are the values ALU stage must use for actual computation. All register addresses are five bits long.

Test the module for various cases, in particular when the register being read may also be written by both the instructions in the next two stages. Submit your simulation output along with the code for FORWARD.

Exercise: Play with the animator interface provide to you and answer the following question.