The devil is in the details -- classic proverb.
In this project you will use verilog to implement the Tomasulo algorithm as described in the textbook (Section 3.3).
In the Tomasulo algorithm, the instruction execution is divided into four stages: fetch, issue, execution, and writeback. The latter three stages access three critical hardware components, namely renaming table, reservation stations (as well as load/store buffers) and common data bus. You will implement (1) the renaming table, (2) reservation stations, and (3) three pipeline stages, and put all components together to form a working processor. You will test your implementation using an example code and submit a project report.
Do the exercise on Tomasulo algorithm (week 4 code examples) before starting the project.
You are provided with basic building blocks, including register file, control units, instruction/data memories, adder, and multiplier. All function units are pipelined with the following operation latencies: load/store two cycles, adder two cycles, multiplication 10 cycles, division 20 cycles. The latencies are the same as in the example in lecture 6 except that the latency of division is reduced.
You are also provided with the full implementations of load buffer (load_buf.v) and CDB arbiter (cdb_arbiter.v). The store buffer implementation is also provided to make the package complete; however, the testing code does not have store instructions. NOTE that load buffer and reservation stations have similar structures and processes, thus you may want to use the former one as a template.
Files rename_table.v and rs_pool.v provide sketch code for the renaming table and reservation station, respectively. Files cpu.v, rename_stage.v and execute_stage.v provide sketch code for the whole processor and the two pipeline stages. Note that the implementation of writeback stage is distributed in rename_stage.v and execute_stage.v.
The example code is provided in inst_mem.mif. It is similar to the example code in lecture 6. Read the file with a text editor to see the actual instructions.
A package named "tomasulo.zip" contains all files. It is downloadable from WebCT. There could be patches for this package, which the instructor would announce in the class and on the web site.
Complete the following program files:
You can make changes to the existing code in those files (and any other files) as long as their overall structures are clear. For the fetch stage, you do not have to implement an instruction queue.
First test each component and pipeline stage individually. Here is an example waveform produced in testing load buffer.
For the whole processor, create a waveform file that includes the contents of renaming table, reservation stations and load buffer. Observe the changes of those contents, which should be consistent to the example in Lecture 6. To observe the values of those components, you need to declare the corresponding Verilog variables with "synthesis preserve" compiler directive:
reg[3:0] rename_table[0:31] /* synthesis preserve */;
Also check the content of register file after execution.
Besides this testing, the instructor may test your implementation using different function unit latencies.
Create a package that contains ALL source code (.v, .mif and .v files), waveform files, and a project report. The report should use PDF format or WORD format. Each group may submit one package.
Your report may include the following contents:
The project is due on 11:55pm Tuesday Oct 7.
There is 10% penalty if one submits after the deadline but before 11:55pm Thursday Oct 9.