LAB 6 CprE 305

We have written Verilog modules from the structural point of view (i.e. gates were our building blocks). For this lab, we will start writing modules from a behavioral point of view. For example, the formula for the carry out of a 1-bit addition may be written as the following: assign carry_out = (a & b) | ((a | b) & carry_in). In addition to “assign” statements, we will also start using “always”, “if . . . else”, and “case” statements to build modules.

1. Create a 1-bit ALU that is capable of performing addition, subtraction, bit-wise AND, bit-wise OR, and set-on-less-than operations.

· The ALU should use a carry-in bit for addition and subtraction. There is an additional input called less to support set-on-less-than instructions.

· Each 1-bit ALU takes 1-bit a and 1-bit b input, a carryin input and produces 1-bit g output, 1-bit p output and 1-bit result. It also takes 3 control inputs,1-bit binv, and two bits op.

· The binv inverts the b input bit if it is 1.

· The 2-input bits op selects output as AND of a and b if they are 00, OR of a and b if they are 01, SUM of a and b if they are 10, and input less if they are 11.

· An additional output called sum is also produced that is the output of SUM of a, b, and carryin.

2. Create a 4-bit ALU that is capable of performing addition, subtraction, bit-wise AND, bit-wise OR, and set-on-less-than instructions on 4-bit operands. The ALU should use 1-bit ALUs and a carry-lookahead module to perform fast addition and subtraction.

3. Test your 4-bit ALU. Your test should be robust – test every instruction type and use inputs that test each 1-bit portion of the 4-bit ALU. Show the results to your TA.