XILINX Project Status
Project File:	xilinx.ise	Current State:	Placed and Routed
Module Name:	Quadratic	Errors:	No Errors
Target Device:	xc4vlx15-12sf363	Warnings:	No Warnings
Product Version:	ISE 8.2.02i	Updated:	Fri Sep 8 22:56:30 2006

 

XILINX Partition Summary

No partition information was found.

 

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of 4 input LUTs	32	12,288	1%
Logic Distribution
Number of occupied Slices	16	6,144	1%
Number of Slices containing only related logic	16	16	100%
Number of Slices containing unrelated logic	0	16	0%
Total Number of 4 input LUTs	32	12,288	1%
Number of bonded IOBs	33	240	13%
Number of BUFG/BUFGCTRLs	1	32	3%
Number used as BUFGs	1
Number used as BUFGCTRLs	0
Number of DSP48s	2	32	6%
Total equivalent gate count for design	275
Additional JTAG gate count for IOBs	1,584

 

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Fri Sep 8 22:53:58 2006	0	0	0
Translation Report	Current	Fri Sep 8 22:55:31 2006	0	0	0
Map Report	Current	Fri Sep 8 22:55:42 2006	0	0	3 Infos
Place and Route Report	Current	Fri Sep 8 22:56:21 2006	0	0	2 Infos
Static Timing Report	Current	Fri Sep 8 22:56:30 2006	0	0	2 Infos
Bitgen Report

 

Secondary Reports
Report Name	Status	Generated
Xplorer Report