Phillip H. Jones III

Contact Information:

Phillip H. Jones III
Assistant Professor

Iowa State University
Dept. of Electrical and Computer Engineering
329 Durham
Ames, Iowa

email: phjones@iastate.edu
homepage: http://www.ece.iastate.edu/~phjones
515-294-9208 (office) 312-933-3891 (mobile)
Office: Durham, Room 329

Research Interests:

Adaptive computing systems
Reconfigurable hardware
Embedded systems
Real-time systems
Fault tolerant systems
Microprocessor off-load hardware for application acceleration
Spaceborne applications

Education:

Ph.D in Computer Engineering at Washington University (St. Louis), May 2008
M.S in Electrical Engineering, University of Illinois (Urbana-Champaign), May 2002
B.S in Electrical Engineering, University of Illinois (Urbana-Champaign), May 1999

Published Papers:

Conference Papers

An Evaluation of a Slice Fault Aware Tool Chain ,
by Adwait Gupte, and Phillip Jones;
Proceedings of Design, Automation, and Test in Europe (DATE), Dresden, Germany, Mar 8-12, 2010. (acceptance rate 30%)
Hotspot Mitigation using Dynamic Partial Reconfiguration for Improved Performance ,
by Adwait Gupte, and Phillip H. Jones;
IEEE International Conference on Reconfigurable Computing and FPGAs (Reconfig), Cancun, Mexico, Dec 9-11, 2009. (acceptance rate 32%)
Towards Hardware Support for Common Sensor Processing Tasks ,
by Adwait Gupte, and Phillip Jones;
15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA) , Beijing, China, August 2009.
Adaptive Thermoregulation for Applications on Reconfigurable Devices,
by Phillip H. Jones, James Moscola, Young H. Cho, and John W. Lockwood;
IEEE International Conference on Field Programmable Logic and Applications (FPL), Amsterdam, Netherlands, Aug 27-29, 2007. (acceptance rate 21%)
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads,
by Phillip H. Jones, Young H. Cho, and John W. Lockwood;
IEEE International Conference on VLSI Design (VLSI Design), Bangalore, India, Jan 6-10, 2007. (acceptance rate 32%)
(Best Paper Award)
An Adaptive Frequency Control Method Using Thermal Feedback for Reconfigurable Hardware Applications,
by Phillip H. Jones, Young H. Cho, and John W. Lockwood;
IEEE International Conference on Field Programmable Technology (FPT), Bangkok, Thailand, Dec 13-15, 2006. (acceptance rate 20%)
A Thermal Management and Profiling Method for Reconfigurable Hardware Applications,
by Phillip H. Jones, John W. Lockwood, and Young H. Cho;
IEEE International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, Aug 28-30, 2006. (acceptance rate 30%)
Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory,
by Roger Chamberlain, John Lockwood, Saurabh Gayen, Richard Hough, and Phillip Jones;
IEEE Intl. Conf. on Microelectronic Systems Education, June, 2005.
Liquid Architecture,
by Phillip Jones, Shobana Padmanabhan, Daniel Rymarz, John Maschmeyer, David V. Schuehler, John W. Lockwood, and Ron K. Cytron;
IEEE International Parallel and Distributed Symposium (IPDPS), Next Generation Software (NGS) Workshop, Santa Fe, New Mexico, April 26, 2004.

Workshop Papers, Short Papers, and Posters

Cycle-Accurate Microarchitecture Performance Evaluation,
by Richard Hough, Phillip Jones, Scott Friedman, Roger Chamberlain, Jason Fritts, John Lockwood, Ron Cytron;
IEEE Workshop on Introspective Architecture (WISA), Austin, TX, February 2006.
Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory,
by Roger Chamberlain, John Lockwood, Saurabh Gayen, Richard Hough, and Phillip Jones;
IEEE Intl. Conf. on Microelectronic Systems Education, June, 2005.
Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures,
by Shobana Padmanabhan, Phillip Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger Chamberlain, Ron K. Cytron, Jason Fritts, and John W. Lockwood;
International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES), Washington DC, September 22, 2004.

Journal Papers

Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures,
by Shobana Padmanabhan, Phillip Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger Chamberlain, Ron K. Cytron, Jason Fritts, and John W. Lockwood;
International Journal of Parallel Programming, Volume 33, Issue 2 - 3, June 2005, Pages 115 - 136.
The Effects of an ARMOR-based SIFT Environment on the Performance and Dependability of User Applications,
K. Whisnant, R.K. Iyer, Z.T. Kalbarczyk, P.H. Jones III, D.A. Rennels, R. Some;
IEEE Transactions on Software Engineering (TSE), Volume 30, Issue 4, April 2004, Pages 257 - 277.

Invited Talks:

"Adaptive Thermoregulation for Applications on Reconfigurable Devices," ECE Department Seminar Invited Talk, Boston University, Boston, MA, December 3, 2007

Appointments

Iowa State University: Assistant Professor (8/2008-Present)
- Teaching
  - Reconfigurable Computing: CPRE 583 (Fall 2010)
    (20 Students = 14 on campus + Distance Education)
    (Teaching Eval: 4.91/5, std:.30, # of replies 11/14)
    (Web address: http://class.ece.iastate.edu/cpre583/)
  - Models and Techniques in Embedded Systems: CPRE 584X (Spring 2010)
    (10 students)
    (Teaching Eval: 4.89/5, std:.33, # of replies 9/10)
    (Web address: http://class.ece.iastate.edu/cpre584/)
  - Reconfigurable Computing: CPRE 583 (Fall 2009)
    (16 Students = 14 on campus + Distance Education)
    (Teaching Eval: 4.58/5, std:.50, # of replies 13/14)
    (Web address: http://class.ece.iastate.edu/cpre583/)
  - Embedded Systems Research Skills: CPRE 594 (Now CPRE 584X)(Spring 2009, with Joseph Zambreno)
    (9 students)
    (Teaching Eval: 4.83/5, std:.41, # of replies 6/9)
    (Web address: http://class.ece.iastate.edu/cpre584/)
  - Reconfigurable Computing: CPRE 583 (Fall 2008)
    (21 students = 11 on campus + Distance Education)
    (Teaching Eval: 4.18/5, std:1.08, # of replies 11/11)
- Students Currently Advised
  - Adwait Gupte, M.S. (2009 - Present): Currently interning with Algo-Logic
  - Sudhanshu Vyas, M.S. (2010 - Present): 1/2 RA (Converting to PhD)
  - Pooja Mhapsekar, M.S. (2010 - Present):1/2 RA
  - Moinuddin Sayed, M.S. (2010 - Present): 1/2 RA
  - Senior Design (with Nicola Elia): MicroCART (2009 - Present)
  - Senior Design (with Joseph Zambreno): NES Emulation (2009 - Present)
- Students Previously Advised
  - Matthew Clausman (with Arun Somani): 1/4 RA for Fall 2009 only
  - Ejiofor Odo (Graduated 12/2009, Distance Education, Intel Corporation):
    Advised final 2 semesters of Creative Component only
  - Ben Armfield (Graduated 12/2008, Distance Education, Rockwell Collins):
    Advised final semester of Creative Component only
- External Funding
  - Funded:
  - (PI) NSF: EArly Grants for Exploratory Research (EAGER) 2010, Funded: $149,900 (1 year)
    - Title: Seamless Integration of Conjoined Cyber-Physical System Properties
    - PI: Phillip Jones (25%), Co-PIs: Joesph Zambreno (25%), Ron Cytron (25%), Chris Gill (25%)
  - (PI) NASA Iowa Experimental Program to Stimulate Competitive Research (EPSCoR) Research Fellowship 2010, Funded: $20K (summer 2010)
  - Pending:
  - Rejected:
  - (Co-PI) NSF: Computing and Communications Foundations (CCF) 2010, Rejected
  - (PI) NSF: Faculty Early Career Development (CAREER) 2010, Rejected
  - (PI) NSF: Cyber-Physical Systems (CPS) 2010, Rejected
  - (PI) NSF: Broading Participation in Engineering (BRIGE) 2010, Rejected
  - (PI) NSF: Cyber-Physical Systems (CPS) 2009, Rejected
- Internal Funding
  - Engineering Fee Task Force (EFTF) 2009: $13K for improving CPRE583 Distance Education infrastructure
  - EFTF (with Joseph Zambreno) 2009: $6K for embedded systems education infrastructure
  - EFTF (with Joseph Zambreno) 2009: $30K for improving high-performance reconfigurable computing education infrastructure
- Current Research Focuses
  - Cyber Physical Systems (Embedded Systems)
  - Thermal/Power aspects of reconfigurable hardware
  - Application acceleration using reconfigurable hardware
- Service Activities
  - ECE Department Head Search Committee: Fall 2009 - Spring 2010
  - Curriculum Committee: Fall 2009 - Present
  - Graduate Admission Committee: Fall 2008 - Spring 2009
- Education Activities
  - IT-Olympics Progamming Competition, volunteer (2009, 2010)
  - MemoCODE design Competition, advisor (2009, 2010)
  - IEEE Extreme Programming Competition, proctor (2010)
- Professional Activities
Washington University: Research Assistant (8/2003 - 1/2008), Postdoc (2/2008 - 7/2008)
- Teaching
  - Introduction to Computing Tools: CSE100 (Fall 2007)
    Note: Course Material developed by Dr. Ronald Loui
- Research
  - Postdoc: Helped develop and test hardware/software codesigns for a biosequence search application (BLAST)
  - Liquid Architecture (NSF-funded): Responsible for the design of hardware infrastructure necessary to integrate a soft-core SPARC-compatible processor (LEON) into a networked Field Programmable Gate Array (FPGA) based platform (FPX), for processor architecture/micro-architecture level research.
  - Digital Systems Laboratory: CSE465 ( Spring 2005)
    - Responsible for hardware infrastructure support
    - Responsible for the design and implementation of most lab assignments
    - Provided general hardware design assistance to students
  - Adaptive computing using temperature feedback for applications implemented in reconfigurable hardware
  - Thermally constrained real-time embedded systems
  - Run-time dynamic reconfiguration on FPGAs
University of Illinois: Research Assistant (9/2000 - 12/2001)
- Developed fault injectors for a distributed network fault injection tool (NFTAPE), for use in performing fault tolerance evaluation experiments.
- Summer 2001, Jet Propulsion Laboratory (JPL-NASA)

Industry Experience

June 2005 - August 2005, Intel Corporation (Hillsboro, OR), Summer Intern
Developed modifications/extensions to CLIPS (an open source expert systems development infrastructure), to build a proof of concept prototype for the management of system reliability at the firmware level.
June 2004 - August 2004, Intel Corporation (Hillsboro, OR), Summer Intern
Developed Linux device driver and made Linux kernel modifications to develop a proof of concept prototype to extend the functionality of IA-64 (Itanium-2) based firmware.
February 2002 - August 2003, Intel Corporation (Chandler, AZ), Intern
- Ran, debugged, and converted regression tests for the validation of a South Bridge I/O chip.
- Performed initial work to interface two validation environments (C++ based and VHDL based)
June 2000 - August 2000, Intel Corporation (Hillsboro, OR), Summer Intern
Developed tests to fault grade several modules of the Pentium 4.
June 1999 - August 1999, Intel Corporation (Hillsboro, OR), Summer Intern
Wrote tests to validate the functionality of modules for a Next Generation I/O (NGIO) networking ASIC.
June 1998 - August 1998, Intel Corporation (Hillsboro, OR), Summer Intern
Ran regression tests, and helped analyze the results of regression test simulations for the functional validation of a networking ASIC.
June 1997 - August 1997, Intel Corporation (Hillsboro, OR), Summer Intern
Used VHDL to design a simple interface to allow a generic micro-controller to read/write status and control registers of a generic device
June 1996 - August 1996, Intel Corporation (Hillsboro, OR), Summer Intern
Initial design of a LED status display, for the front panel of a 10/100 Ethernet system

Honors:

Best Paper Award, IEEE International Conference on VLSI Design (VLSI Design), 2007
Graduate Engineering Minority (GEM) Fellowship (1999-2000, 2003-2004)
Intel Minority Scholarship (1996-1999)
High School Perfect Attendance (1992-1995)

Other Activities:

University of Illinois Gymnastics team member (1996-1999)
Capoeira Brazil Martial Arts group member (2003-2005)
St. Louis Ultimate Frisbee League Summer/Fall (2006, 2007,2008)
Des Moines Ultimate Frisbee League Summer (2009, 2010)

Skill Set:

Programming Languages

Proficient in VHDL, C++, C, 80x86 assembler, Perl.
Some experience with ACE middleware, Spice, Verilog, AWK

System Level Development

Experience with:

System on Chip Design (FPGA-based): Soft-core processor (LEON) centric, Network packet processing
Socket programming
Integration of special purpose hardware via the SPARC V8 coprocessor interface
Linux device driver development
SPARC and PowerPC instruction sets

Some experience with: CMOS circuit design, Analog circuit design
Background in:

Embedded real-time system design
Fault tolerant system design

Communication Protocols

Familiar with: TCP, UDP, IP, RTP, PCI, PCI-X, PCI-Express, USB, Ethernet, Pentium-4 front-side bus

General Tools

Familiar with: Oscilloscopes, Logic Analyzers, Network/Spectrum analyzers

Course Work:

Computer Systems Performance Analysis, Computer Architecture, Reliable Computer Systems, Digital Systems Design for Testability, CMOS Circuit Analysis and Design, Computer Algorithms, System on Chip Design, Operating Systems, Network Protocols, Data Security (e.g. cryptography algorithms), Multimedia Computing and Networking, Introduction to Languages and the Theory of Computation, Artificial Intelligence, Logic Design, Data Structures, Analog Circuit Analysis and Design, Linear Systems and Signals Analysis, IC Fabrication, Solid-State Electronics, Digital Signal Processing, Radio Frequency Circuit Design, Advanced Electromagnetics, Advanced calculus, Differential equations, Linear algebra, Quantum physics.

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Last modified: Thu Jan 24 10:43:56 CST 2008