Digital System Design using VHDL and CPLD (*)

       *Partial support for this work was provided by the National Science
       Foundation's Division of Undergraduate Education through grant
       DUE-9650347 and by the Altera Corporation's Altera University Grant.


               Morris Chang (chang@charlie.iit.edu)

Course Objectives

This six-day short course is intended for introducing digital system design with the 
latest technologies to our senior and graduate students (or engineers). In order to 
provide a smooth transition from the academic abstractions to the engineering practice, 
the systematic introduction is presented with commercially available CAD tools. The 
innovative teaching methodology [1] and the hands-on laboratory assignments accelerate
and reinforce our students' learning. A tutorial workshop based on similar material has
been presented to international professions at IEEE International ASIC Conference at 
Austin, Texas, in September 1995. 

[1] Morris Chang, "Teaching Top-Down Design using VHDL and CPLD," Proceedings 
of IEEE Frontiers in Education Conference, Salt Lake City, Utah, November 6-9, 1996. 

Semester Credit Hours: 2

Prerequisites: 

A working knowledge of logic design at the level of ECE 218 (Digital Systems).
Familiarity with a computer programming language. 

Course Notes: "CS-471 - Introduction to VHDL," by Morris Chang, 1997, IIT.

Reference: "VHDL," 2nd edition, by Douglas Perry, 1994, McGraw-Hill.

Details:       Proposed Schedule: August 1, 1997 - August 8, 1997
               Ideal Class size: 16 students ( with 16 computers)
               Max. Class size: 32 students (2 students per computer)
               Computer Facility: Pentium based PC with at least 16MB 
               memory and CD-ROM driver. Software- Altera's Maxplus2 7.10 or newer. 
               (The software will be provided by instructor).

Course Description: 

VHDL (VHSIC Hardware Description Language) has become an important standard for 
describing digital systems for simulation and synthesis. This short course will 
introduce the syntax and semantics of the VHDL language and its use in simulation
and synthesis using the Altera design environment. The course begins with a brief summary
of the VHDL syntax and the presentation of several examples of hardware modelling, 
including combinational logic, sequential logic, and finite state machines. Applications of 
VHDL to top-down design are discussed as well as logic synthesis using libraries. Lecture 
material will be reinforced by a series of hands-on lab assignments in which students 
write, simulate, and synthesize VHDL descriptions. 

Introduction

In recent years, CPLDs (Complex Programmable Logic Devices) have increased 
dramatically in capacity and complexity. CPLDs with 100K gates are available in today's 
technology. To cope with the complex design, higher level of abstraction and hierarchy in 
design description have become desirable to digital systems designers. Today, system-
level logic design is most likely a team work, forcing modular and hierarchical design 
approach. Moreover, exploiting many technology (implementation) options without 
translation of the source design description is an increasingly important requirement. The 
IEEE-standard (i.e. IEEE-1076) VHDL language addresses these needs.

VHDL can be used to describe hardware from the abstract to the concrete level. 
Many of the EDA (Electronic Design Automation) vendors are standardizing on VHDL as 
input and output from their tools. These tools include simulation tools, synthesis tools, 
layout tools, testing tools, etc. Due to the recent advances in high-level systhesis
tools, the text-based design entry has gained increasing popularity in the ASIC design.
This short course will introduce VHDL as the design entry in the CPLD design environment.
We will focus on how to write VHDL that can be processed by synthesis tools.

This short course will provide a hands-on tutorial on using VHDL as the design 
entry in Altera's MAXPLUS2. The design will be systhesized to the CPLD in the class.

Course Outline:

Day 1: This session will introduce most of the basic VHDL constructs such as entity and 
architecture declarations, data types, operators and concurrent statements. Lab: 
Altera tool (Maxplus2) overview, VHDL specification, simulation and hardware 
synthesis of combinational logic. 

Day 2: This session covers processes, variables, sequential statements, wait statements. 
Specific topics include: register inference, finite-state machine and algorithmic 
state machine specification, simulation and synthesis. Lab: VHDL specification, 
simulation and hardware synthesis of sequential logic. 

Day 3: This session covers VHDL constructs that allow the structural interconnection of 
components and the encapsulation of such components in modular libraries. The 
VHDL constructs include: component declaration and instantiation, generate 
statements, package declarations, functions. Lab: writing, simulating and 
synthesizing structural VHDL. 

Day 4:This session will introduce advanced synthesis topics to facilitate design 
specification, design reuse and efficient synthesis using VHDL; use of 
macrofunction libraries in Altera, high-level optimizations for synthesis, Library of 
Parameterized Modules (LPMs). Lab: efficient description and synthesis of a simple 
datapath controller system using libraries. 

Day 5: This session covers advanced topics in VHDL and CPLD: introduction to the 
architecture of CPLDs; timing analysis tools; floor plan editor; examples in top-
down design methodology using VHDL; the VHDL portability issues in the 
synthesis tools. Lab: algorithm mapping and top-down design.

Day 6: This session presents a case study of designing a simple RISC microprocessor in 
VHDL and CPLD. The design considerations and trade-offs of each component in 
a RISC CPU is discussed. The limitation of current technologies and possible 
directions of future development is presented. Lab: Designing ALU, shifter, 
register file and decoder/controller for MIPS 2000 architecture. 



About the Instructor: 

Morris Chang received the B.S. degree in electrical engineering from Tatung 
Institute of Technology, Taiwan, the M.S. degree in electrical engineering and the Ph.D. 
degree in computer engineering from North Carolina State University in 1983, 1986 and 
1993, respectively.

He has more than ten years' experience in the field of design and test of electronic 
systems, beginning with his first job as analog IC designer for Texas Instruments in 1983. 
During his two years as a Member of Technical Staff at the Microelectronics Center of 
North Carolina (MCNC), he initiated the research on linking digital design to test. When 
he was with AT&T Bell Laboratories (1988-1990), he worked in the Hobbit (AT&T's low-
power 32-bit RISC microprocessor) team on the architectural design and verification. In 
1995, he joined the Computer Engineering Program and the Department of Computer 
Science at Illinois Institute of Technology, Chicago, IL, where he is currently an
Assistant Professor. 

Dr. Chang has taught undegraduate and graduate level courses in the area of 
computer architecture and digital systems at Rochester Institute of Technology and Illinois 
Institute of Technology. His recent project on "A Laboratory for Integrating Digital 
Design and Test" is funded by National Science Foundation. His research interests include 
computer architecture, object-oriented programming languages, hardware description 
languages, memory management and VLSI testing. He has conducted research under contracts
from NSF.

Dr. Chang has been serving on the technical committee of IEEE International 
ASIC Conference since 1994. He was the Secretary and Treasurer of the 1995 ASIC 
Conference, Austin, Texas. He was a member of the Organizing Committee of 1996 ASIC 
Conference.